AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 49

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.5.18
Datasheet
Note:
PAM0 - Programmable Attribute Map 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h- 0FFFFFh. The processor allows programmable memory attributes on 13
Legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) Registers are used to support these features.
Cacheability of these areas is controlled via the MTRR registers in the P6 processor. Two
bits are used to specify memory attributes for each memory segment. These bits apply
to both host accesses and PCI initiator accesses to the PAM areas. These attributes are:
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
The processor may hang if DMI originated access to Read Disabled or Write Disabled
PAM segments occur (due to a possible IWB to non-DRAM).
•
•
63:36
35:12
11:1
Bit
RE - Read Enable - When RE = 1, the CPU read accesses to the corresponding
memory segment are claimed by the processor and directed to main memory.
Conversely, when RE = 0, the host read accesses are directed to PCI_A.
WE - Write Enable - When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the processor and directed to main memory.
Conversely, when WE = 0, the host write accesses are directed to PCI_A.
0
Access
RW-L
RW-L
RO
RO
0000000h
000000h
Default
Value
000h
0b
0/0/0/PCI
90h
00h
RO; RW-L;
8 bits
RST/
PWR
Core
Core
Core
Core
Reserved (DMIBAR_rsv)
DMI Base Address (DMIBAR)
This field corresponds to Bits 35:12 of the
base address DMI configuration space.
BIOS will program this register resulting
in a base address for a 4-KB block of
contiguous memory address space. This
register ensures that a naturally aligned
4-KB space is allocated within the first 64
GB of addressable memory space. System
Software uses this base address to
program the DMI register set.
Reserved
Reserved
Description
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