AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 47

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
Datasheet
63:36
35:28
Bit
27
26
Access
RW-L
RW-L
RW-L
reserved above TOLUD) is not greater than the 64-bit addressable limit of 64GB. In
general system implementation and number of PCI/PC Express/PCI-X buses supported
in the hierarchy will dictate the length of the region.
RO
0000000h
Default
Value
0Eh
0b
0b
RST/
PWR
Core
Core
Core
Core
Reserved (DMIBAR_rsv)
PCI Express Base Address (PCIEXBAR)
This field corresponds to bits 35 to 28 of the base address
for PCI Express enhanced configuration space. BIOS will
program this register resulting in a base address for a
contiguous memory address space; size is defined by bits
2:1 of this register.
This Base address shall be assigned on a boundary
consistent with the number of buses (defined by the
Length field in this register) above TOLUD and still within
64-bit addressable memory space. The address bits
decoded depend on the length of the region defined by
this register.
The address used to access the PCI Express configuration
space for a specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device
Number * 32KB + Function Number * 4KB
Remember that this address is the beginning of the 4KB
space that contains both the PCI compatible configuration
space and the PCI Express extended configuration space.
128MB Base Address Mask (128ADMSK):
This bit is either part of the PCI Express Base Address (R/
W) or part of the Address Mask (RO, read 0b), depending
on the value of bits 2:1 in this register.
64MB Base Address Mask (64ADMSK):
This bit is either part of the PCI Express Base Address (R/
W) or part of the Address Mask (RO, read 0b), depending
on the value of bits 2:1 in this register.
Description
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