AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 35

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
Datasheet
Bit
6
5
4
3
2
1
0
Access
RW
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
1b
1b
0b
(Sheet 2 of 2)
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Parity Error Enable (PERRE)
Controls whether or not the Master Data
Parity Error bit in the PCI Status register
can bet set.
0: Master Data Parity Error bit in PCI
Status register can NOT be set.
1: Master Data Parity Error bit in PCI
Status register CAN be set.
VGA Palette Snoop Enable
(VGASNOOP)
The processor does not implement this
bit and it is hardwired to a 0. Writes to
this bit position have no effect.
Memory Write and Invalidate Enable
(MWIE)
The processor will never issue memory
write and invalidate commands. This bit
is therefore hardwired to 0. Writes to this
bit position will have no effect.
Special Cycle Enable (SCE)
The processor does not implement this
bit and it is hardwired to a 0. Writes to
this bit position have no effect.
Bus Master Enable (BME)
The processor is always enabled as a
master. This bit is hardwired to a “1”.
Writes to this bit position have no effect.
Memory Access Enable (MAE)
he processor always allows access to
main memory. This bit is not
implemented and is hardwired to 1.
Writes to this bit position have no effect.
I/O Access Enable (IOAE)
This bit is not implemented in the
processor and is hardwired to a 0. Writes
to this bit position have no effect.
Description
35