AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 92

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.19
92
31:24
23:16
15:8
7:0
Bit
Access
RW-L
RW-L
RW-L
RW-L
C0DTAEW - Channel 0 DRAM Rank Throttling Active Event
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8 bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks. IMC implements 4 independent filters, one per rank. During a given clock, IMC
asserts a command to the DRAM (via CSB assertion). Based on the command type, one
of the weights specified in this register is added to the appropriate weight specified in
C0DTPEW and input to the filter. All bits in this register can be locked by the DTLOCK bit
in the C0DTC register.
Default
Value
00h
00h
00h
00h
RST/PWR
Core
Core
Core
Core
Additive Weight for ODT (AWODT):
This value is added to the total weight of a Rank if ODT
on that rank is asserted.
NOTE: This value should reflect whether the DRAMs
Weight for Any Open Page During Active
(WAOPDA):
This value is input to the filter if, during the present
clock, the corresponding rank has any pages open and is
not in power down (Page Open Idle). The value
programmed here is IDD3N from the JEDEC spec.
All Banks Precharge Active (ABPA):
This value is input to the filter if, during the present
clock, the corresponding rank has all banks precharged
but is not in power down (Page Close Idle). The value
programmed here is IDD2N from the JEDEC spec.
All Banks Precharge Power Down (ABPPD):
This value is input to the filter if, during the present
clock, the corresponding rank has all banks precharged
and is powered down (Page Close Power Down). The
value programmed here is IDD2P from the JEDEC spec.
0/0/0/MCHBAR
2AC-2B3h
0000000000000000h
64 bits
RO; RW-L;
have been programmed for 75 or 150 ohm
termination.
Processor Configuration Registers
Description
Datasheet