AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 80

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.8
80
15:11
10:6
5:2
1:0
Bit
Access
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Precharge Registers.
RW
RW
RW
RO
15:8
7:0
Bit
Default
00000b
00000b
Value
0000b
Access
00b
RW-L
RW-L
RST/PWR
Default
Core
Core
Core
Core
Value
00h
00h
Reserved
Write To PRE Delayed (C0sd_cr_wr_pchg):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and PRE
commands to the same rank-bank.Corresponds to tWR at
DDR Spec.
READ To PRE Delayed (C0sd_cr_rd_pchg):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and PRE
commands to the same rank-bank
PRE To PRE Delayed (C0sd_cr_pchg_pchg):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two PRE commands to
the same rank.
0/0/0/MCHBAR
250-251h
0000h
16 bits
RST/PWR
RO; RW;
Core
Core
Channel 0 DRAM Rank-3 Attributes
(C0DRA3):
This register defines DRAM page size/
number-of-banks for rank3 for given
channel
See table in register description for
programming
Channel 0 DRAM Rank-2 Attributes
(C0DRA2):
This register defines DRAM page size/
number-of-banks for rank2 for given
channel
See table in register description for
programming
Processor Configuration Registers
Description
Description
Datasheet