AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 60

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.29
60
Bit
7
6
5
4
3
Access
RW-L
RWC
ESMRAMC - Extended System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
RO
RO
RO
Default
Value
0b
0b
1b
1b
1b
RST/
PWR
Core
Core
Core
Core
Core
Enable High SMRAM (H_SMRAME):
Controls the SMM memory space location (i.e. above 1 MB
or below 1 MB) When G_SMRAME is 1 and H_SMRAME is
set to 1, the high SMRAM memory space is enabled.
SMRAM accesses within the range 0FEDA0000h to
0FEDBFFFFh are remapped to DRAM addresses within the
range 000A0000h to 000BFFFFh. Once D_LCK has been
set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR):
This bit is set when CPU has accessed the defined memory
ranges in Extended SMRAM (High Memory and T-segment)
while not in SMM space and with the D-OPEN bit = 0. It is
software's responsibility to clear this bit. The software
must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE):
This bit is forced to '1' by the processor.
L1 Cache Enable for SMRAM (SM_L1):
This bit is forced to '1' by the processor.
L2 Cache Enable for SMRAM (SM_L2):
This bit is forced to '1' by the processor.
0/0/0/PCI
9Eh
38h
8 bits
RW-L; RWC; RO;
Processor Configuration Registers
Description
Datasheet