AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 153

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.10.4
Datasheet
10:9
Bit
Bit
15
14
13
12
11
0
8
7
Access
Access
RW
PCISTS2 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that
has been set by the IGD.
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
00b
0b
0b
0b
0b
0b
0b
0b
1b
RST/PWR
RST/PWR
FLR, Core
Core
Core
Core
Core
Core
Core
Core
Core
I/O Access Enable (IOAE):
accesses.
Detected Parity Error (DPE):
hardwired to 0.
Signaled System Error (SSE):
hardwired to 0.
Received Master Abort Status (RMAS):
hardwired to 0.
Received Target Abort Status (RTAS):
hardwired to 0.
Signaled Target Abort Status (STAS):
semantics.
DEVSEL Timing (DEVT):
Master Data Parity Error Detected (DPD):
(and the IGD does not do any parity detection), this bit is
hardwired to 0.
Fast Back-to-Back (FB2B):
the transactions are not to the same agent.
This bit controls the IGD's response to I/O space
0:Disable.
1:Enable.
Since the IGD does not detect parity, this bit is always
The IGD never asserts SERR#, therefore this bit is
The IGD never gets a Master Abort, therefore this bit is
The IGD never gets a Target Abort, therefore this bit is
Hardwired to 0. The IGD does not use target abort
N/A. These bits are hardwired to “00”.
Since Parity Error Response is hardwired to disabled
Hardwired to 1. The IGD accepts fast back-to-back when
0/2/1/PCI
6-7h
0090h
16 bits
RO;
Description
Description
153