AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 68

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.37
68
ERRCMD - Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the processor responses to various system errors. Since the
processor does not have an SERRB signal, SERR messages are passed from the
processor to the chipset over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device #0 via the PCI Command register.
15:12
Bit
11
10
9
8
Access
RW
RW
RW
RO
RO
Default
Value
0h
0b
0b
0b
0b
0/0/0/PCI
CA-CBh
0000h
16 bits
RO; RW;
RST/
PWR
Core
Core
Core
Core
Core
Reserved
SERR on processor Thermal Sensor
Event (TSESERR):
1: The processor generates a DMI SERR
special cycle when bit 11 of the ERRSTS
is set. The SERR must not be enabled at
the same time as the SMI for the same
thermal sensor event.
0: Reporting of this condition via SERR
messaging is disabled.
Reserved
SERR on LOCK to non-DRAM Memory
(LCKERR):
1: The processor will generate a DMI
SERR special cycle whenever a CPU lock
cycle is detected that does not hit DRAM.
0: Reporting of this condition via SERR
messaging is disabled.
SERR on DRAM Refresh Timeout
(DRTOERR):
1: The processor generates a DMI SERR
special cycle when a DRAM Refresh
timeout occurs.
0: Reporting of this condition via SERR
messaging is disabled.
Processor Configuration Registers
Description
Datasheet