AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 64

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.34
64
Note:
This register is locked and becomes Read Only when the D_LCK bit in the SMRAM
register is set.
TSEGMB - TSEG Memory Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory by subtracting the TSEG size (PCI Device 0 offset 9E bits 02:01)
from graphics GTT stolen base (PCI Device 0 offset A8 bits 31:20).Once D_LCK has
been set, these bits becomes read only.
31:20
31:20
19:0
19:0
Bit
Bit
Access
Access
RW-L
RW-L
RO
RO
Default
Default
00000h
00000h
Value
Value
000h
000h
0/0/0/PCI
AC-AFh
00000000h
32 bits
RST/PWR
RO; RW-L;
RST/
PWR
Core
Core
Core
Core
Graphics Base of Stolen Memory
(GBSM):
This register contains bits 31 to 20 of the
base address of stolen DRAM memory.
BIOS determines the base of graphics
stolen memory by subtracting the GTT
graphics stolen memory size (PCI Device
0 offset 52 bits 9:8) from the graphics
stolen memory base (PCI Device 0 offset
A4 bits 31:20).
Note: This register is locked and becomes
Read Only when the D_LCK bit in the
SMRAM register is set.
Reserved
TESG Memory base (TSEGMB):
This register contains bits 31 to 20 of the
base address of TSEG DRAM memory.
BIOS determines the base of TSEG
memory by subtracting the TSEG size (PCI
Device 0 offset 9E bits 02:01) from
graphics GTT stolen base (PCI Device 0
offset A8 bits 31:20).
Once D_LCK or MSLOCK has been set,
these bits becomes read only.
Reserved
Processor Configuration Registers
Description
Description
Datasheet