AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 91

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AU80610004653AAS LBMG

Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet

Specifications of AU80610004653AAS LBMG

Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Processor Configuration Registers
1.6.18
Datasheet
18:16
15:8
7:0
Bit
Access
RW-L
RW-L
RW-L
C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8 bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks. IMC implements 4 independent filters, one per rank. All bits in this register can
be locked by the DTLOCK bit in the C0DTC register.
Default
Value
000b
00h
00h
RST/PWR
Core
Core
Core
Time Constant (TC):
Weighted Average Bandwidth Limit (WAB):
Average weighted bandwidth allowed per clock during for
bandwidth based throttling. Memory Controller does not
allow any transactions, except Internal Gfx and Isoch
cycles, to proceed on the System Memory bus if the
output of the filter equals or exceeds this value.
Weighted Average Thermal Limit (WAT):
Average weighted bandwidth allowed per clock during for
thermal sensor enabled throttling. IMC does not allow
any transactions, except Internal Gfx and Isoch cycles,
to proceed on the System Memory bus if the output of
the filter equals or exceeds this value.
0/0/0/MCHBAR
2A8-2ABh
00000000h
32 bits
RW-L;
000:2^28 Clocks
001:2^27 Clocks
010:2^26 Clocks
011:2^25 Clocks
1XX:Reserved.
Description
91

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