AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 152

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.10.3
152
15:11
Bit
10
9
8
7
6
5
4
3
2
1
Access
PCICMD2 - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
RST/PWR
FLR, Core
FLR, Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
VGA Palette Snoop Enable (VGASNOOP): This bit is
hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write
and invalidate commands.
Reserved
Reserved
Fast Back-to-Back (FB2B):
Not Implemented. Hardwired to 0.
SERR Enable (SERRE):
Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP):
Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE):
Not Implemented. Hardwired to 0. Since the IGD belongs
to the category of devices that does not corrupt
programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and
continues with normal operation.
Special Cycle Enable (SCE):
This bit is hardwired to 0. The IGD ignores Special
cycles.
Bus Master Enable (BME):
0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI compliant master.
Memory Access Enable (MAE):
This bit controls the IGD's response to memory space
accesses.
0: Disable.
1: Enable.
0/2/1/PCI
4-5h
0000h
16 bits
RO; RW;
Processor Configuration Registers
Description
Datasheet