AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 28

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.6
1.2.7
28
Note:
DMI Interface read accesses to the GMADR range are not supported therefore will have
no address translation concerns. DMI Interface reads to GMADR will be remapped to
address 000C_0000h. The read will complete with UR (unsupported request)
completion status.
GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640K-1M). Thus, they will be invalid and go to address
000C_0000h, but that isn’t specific to DMI; it applies to CPU or internal graphics
engines. Also, since the GMADR snoop would not be directly to the SMM space, there
wouldn’t be a writeback to SMM. In fact, the writeback would also be invalid (because it
uses the same translation) and go to address 000C_0000h.
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into DRAM memory. Typically this is done to allow ROM code to execute
more rapidly out of main DRAM. ROM is used as read-only during the copy process
while DRAM at the same time is designated write-only. After copying, the DRAM is
designated read-only so that ROM is shadowed. CPU bus transactions are routed
accordingly.
I/O Address Space
The processor does not support the existence of any other I/O devices beside itself. The
processor generates DMI cycles for all processor I/O accesses that it does not claim.
Within the host bridge the processor contains two internal registers in the CPU I/O
space, Configuration Address register (CONFIG_ADDRESS) and the Configuration Data
register (CONFIG_DATA). These locations are used to implement a configuration space
access mechanism.
The CPU allows 64 k+3 bytes to be addressed within the I/O space. The processor
propagates the CPU I/O address without any translation on to the destination bus and
therefore provides addressability for 64 k+3 byte locations.
The upper three locations can be accessed only during I/O address wrap-around when
CPU bus HAB_16 address signal is asserted. HAB_16 is asserted on the CPU bus
whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh.
HAB_16 is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI bus unless they fall within the PCI Express I/O address range as
defined by the mechanisms explained below. I/O writes are not posted. Memory writes
to ICH or PCI Express are posted. The PCICMD1 register can disable the routing of I/O
cycles to PCI Express.
Processor Configuration Registers
Datasheet