AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 4

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
1.6
1.7
1.5.35 TOLUD - Top of Low Usable DRAM.............................................................65
1.5.36 ERRSTS - Error Status .............................................................................66
1.5.37 ERRCMD - Error Command.......................................................................68
1.5.38 SMICMD - SMI Command.........................................................................69
1.5.39 SKPD - Scratchpad Data ..........................................................................70
1.5.40 CAPID0 - Capability Identifier ...................................................................70
MCHBAR ...........................................................................................................74
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR......................................................82
1.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ ...................................................83
1.6.12 C0CYCTRKREFR - Channel 0 CYCTRK REFR.................................................84
1.6.13 C0CKECTRL - Channel 0 CKE Control .........................................................84
1.6.14 C0REFRCTRL - Channel 0 DRAM Refresh Control .........................................86
1.6.15 C0ODTCTRL - Channel 0 ODT Control ........................................................88
1.6.16 C0GTEW - Channel 0 Memory Controller Throttling Event Weights. ................89
1.6.17 C0GTC - Channel 0 Memory Controller Throttling Control .............................90
1.6.18 C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event..........................91
1.6.19 C0DTAEW - Channel 0 DRAM Rank Throttling Active Event ...........................92
1.6.20 C0DTC - Channel 0 DRAM Throttling Control...............................................94
1.6.21 TSC1 - Thermal Sensor Control 1 ..............................................................95
1.6.22 TSS - Thermal Sensor Status ...................................................................97
1.6.23 TR - Thermometer Read ..........................................................................98
1.6.24 TSTTP - Thermal Sensor Temperature Trip Point .........................................99
1.6.25 DACGIOCTRL1 - DAC/GPIO Control Register 1 .......................................... 100
1.6.26 PMCFG - Power Management Configuration .............................................. 100
1.6.27 PMSTS - Power Management Status ........................................................ 102
DMIBAR ......................................................................................................... 103
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
1.7.8
1.7.9
1.7.10 DMIVC1RSTS - DMI VC1 Resource Status................................................. 111
1.7.11 DMIRCLDECH - DMI Root Complex Link Declaration................................... 112
1.7.12 DMI Element Self Description ................................................................. 112
1.7.13 DMILE1D - DMI Link Entry 1 Description .................................................. 113
1.7.14 DMILE1A - DMI Link Entry 1 Address ....................................................... 114
1.7.15 DMILE2D - DMI Link Entry 2 Description .................................................. 115
1.7.16 DMILE2A - DMI Link Entry 2 Address ....................................................... 116
1.7.17 DMIRCILCECH - DMI Root Complex Internal Link Control............................ 116
1.7.18 DMILCAP - DMI Link Capabilities ............................................................. 117
CHDECMISC - Channel Decode Misc ..........................................................75
C0DRB0 – Channel 0 DRAM Rank Boundary Address 0 .................................76
C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................................77
C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................................77
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................................78
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ..........................................78
C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute ..........................................79
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ...............................................80
C0CYCTRKACT - Channel 0 CYCTRK ACT ....................................................81
DMIVCECH - DMI Virtual Channel Enhanced Capability ............................... 104
DMIPVCCAP1 - DMI Port VC Capability Register 1 ...................................... 105
DMIPVCCAP2 - DMI Port VC Capability Register 2 ...................................... 105
DMIPVCCTL - DMI Port VC Control........................................................... 106
DMIVC0RCAP - DMI VC0 Resource Capability ............................................ 106
DMIVC0RCTL0 - DMI VC0 Resource Control .............................................. 107
DMIVC0RSTS - DMI VC0 Resource Status................................................. 108
DMIVC1RCAP - DMI VC1 Resource Capability ............................................ 109
DMIVC1RCTL1 - DMI VC1 Resource Control .............................................. 109
Datasheet