AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 16

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.1.2.1
1.2.1.2.2
1.2.1.3
16
Table 1-1. Expansion Area Memory Segments
Compatible SMRAM Address Range (A_0000h-B_FFFFh)
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are
routed to physical system DRAM at 000A 0000h - 000B FFFFh. Non-SMM-mode CPU
accesses to this range are considered to be to the Video Buffer Area as described
above. PCI Express and DMI originated cycles to enabled SMM space are not allowed
and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA
device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and will
master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h-B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,
or the DMI (depending on configuration bits). Since the monochrome adapter may be
mapped to any one of these devices, the IMC must decode cycles in the MDA range
(000B_0000h - 000B_7FFFh) and forward either to IGD, PCI Express, or the DMI. This
capability is controlled by a VGA steering bits and the legacy configuration bit (MDAP
bit). In addition to the memory range B0000h to B7FFFh, the IMC decodes IO cycles at
3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either IGD, PCI
Express, and/or the DMI.
Expansion Area (C_0000h-D_FFFFh)
This 128-KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight,
16-KB segments. Each segment can be assigned one of four Read/Write states: read-
only, write-only, read/write, or disabled. Typically, these blocks are mapped through
IMC and are subtractively decoded to ISA space. Memory that is disabled is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Memory Segments
0D8000H - 0DBFFFH
0C8000H - 0CBFFFH
0D0000H - 0D3FFFH
0D4000H - 0D7FFFH
0DC000H - 0DFFFFH
0C0000H - 0C3FFFH
0C4000H - 0C7FFFH
0CC000H - 0CFFFFH
Attributes
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Comments
Processor Configuration Registers
Datasheet