AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 37

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
Datasheet
10:9
2:0
Bit
8
7
6
5
4
3
Access
RWC
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
00b
0b
1b
0b
0b
1b
0b
(Sheet 2 of 2)
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
DEVSEL Timing (DEVT):
These bits are hardwired to “00”. Writes
to these bit positions have no affect.
Device 0 does not physically connect to
PCI_A. These bits are set to “00” (fast
decode) so that optimum DEVSEL timing
for PCI_A is not limited by the processor.
Master Data Parity Error Detected
(DPD):
This bit is set when DMI received a
Poisoned completion from chipset.
This bit can only be set when the Parity
Error Enable bit in the PCI Command
register is set.
Fast Back-to-Back (FB2B):
This bit is hardwired to 1. Writes to these
bit positions have no effect. Device 0
does not physically connect to PCI_A.
This bit is set to 1 (indicating fast back-
to-back capability) so that the optimum
setting for PCI_A is not limited by the
processor.
Reserved
66 MHz Capable:
Does not apply to PCI Express. Must be
hardwired to 0.
Capability List (CLIST):
This bit is hardwired to 1 to indicate to
the configuration software that this
device/function implements a list of new
capabilities. A list of new capabilities is
accessed via register CAPPTR at
configuration address offset 34h. Register
CAPPTR contains an offset pointing to the
start address within configuration space
of this device where the Capability
Identification register resides.
Reserved
Reserved
Description
37