AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 148

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.9.37
148
15:8
7:0
Bit
Access
RW
RW
ASLS – ASL Storage
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
register usage must be worked out in common between System BIOS and driver
software, but storage for switching/indicating up to 6 devices is possible with this
amount.
detectable yes or no, VGA/NonVGA), one bit for _DGS (enable/disable requested), and
two bits for _DCS (enabled now/disabled now, connected or not).
This software scratch register only needs to be read/write accessible. The exact bit
For each device, the ASL control method with require two bits for _DOD (BIOS
31:0
Bit
Default
Value
00h
00h
Access
RW
RST/PWR
00000000h
Core
Core
Default
Value
ASLE Scratch Trigger 1 (AST1):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16- bit or 32-bit write, only one
interrupt is generated in common.
ASLE Scratch Trigger 0 (AST0):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common. The exact usage of
these bytes, including whether they are addressed as
bytes, words, or as a dword, is not predetermined but
subject to change by driver and System BIOS teams
(acting in unison).
When written, this scratch byte triggers an interrupt
When written, this scratch byte triggers an interrupt
0/2/0/PCI
FC-FFh
00000000h
32 bits
RST/PWR
RW;
Core
Device Switching Storage (DSS):
device switching.
Software controlled usage to support
Processor Configuration Registers
Description
Description
Datasheet