AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 25

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.2.5
1.2.5.1
Datasheet
Note:
Note:
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The processor supports: Compatible SMRAM (C_SMRAM), High Segment
(HSEG), and Top of Memory Segment (TSEG). System Management RAM space
provides a memory area that is available for the SMI handlers and code and data
storage. This memory resource is normally hidden from the system OS so that the
processor has immediate access to this memory space upon entry to SMM. IMC
provides three SMRAM options:
The above 1-MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
DMI masters are not allowed to access the SMM space.
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to
access SMM space. DRAM SMM space is defined as the range of physical DRAM memory
locations containing the SMM code. SMM space can be accessed at one of three
transaction address ranges: Compatible, High and TSEG. The Compatible and TSEG
SMM space is not remapped and therefore the addressed and DRAM SMM space is the
same address range. Since the High SMM space is remapped the addressed and DRAM
SMM space are different address ranges.
The High DRAM space is the same as the Compatible Transaction Address space.
Table 1-5
These abbreviations are used later in the table describing SMM Space Transaction
Handling.
•
•
•
•
•
•
Below 1-MB option that supports compatible SMI handlers.
Above 1-MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
stolen memory.
Compatible Transaction Address (Adr C)
High Transaction Address (Adr H)
TSEG Transaction Address (Adr T)
describes three unique address ranges:
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