HD6432670 Hitachi, HD6432670 Datasheet - Page 106

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
7
6
5
4
3
2
1
0
Note: Mode 3 is available only in the F-ZTAT version of H8S/2678R Series.
Rev. 2.0, 04/02, page 60 of 906
Bit Name
MACS
FLSHE
EXPE
RAME
Initial Value
1
1
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
Reserved
The initial value should not be modified.
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction
Reserved
The initial value should not be modified.
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read/written to. If this bit is cleared to 0, the
flash memory control registers are not selected. At this
time, the contents of the flash memory control registers
are maintained. This bit should be written to 0 other
than flash memory version.
0: Flash memory control registers are not selected for
1: Flash memory control registers are selected for area
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4 to 6, this bit is fixed at 1 and
cannot be modified. In mode 3* and 7, this bit has an
initial value of 0, and can be read and written.
Writing of 0 to EXPE when its value is 1 should only be
carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
area H'FFFFC8 to H'FFFFCB
H'FFFFC8 to H'FFFFCB