HD6432670 Hitachi, HD6432670 Datasheet - Page 256

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.7.12
With synchronous DRAM, in addition to full access (normal access) in which data is accessed by
outputting a row address for each access, burst access is also provided which can be used when
making consecutive accesses to the same row address. This access enables fast access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Rev. 2.0, 04/02, page 210 of 906
Burst Operation
(Address shift size set to 8 bits)
DCTL
Figure 6.51 Example of DQMU and DQML Byte Control
This LSI
Notes: 1. Bank control is not available.
2. The CKE and
3. The
D15 to D0
I/O PORT
(SDRAMø)
(DQMU)
(DQML)
(
(
(CKE)
A23
A21
A12
A11
A10
(
A9
A8
A7
A6
A5
A4
A3
A2
A1
pin must be fixed to 0 before accessing synchronous DRAM.
)
)
)
pins must be fixed to 1 when the power supply is input.
16-Mbit synchronous DRAM
1 Mword × 16 bits × 4-bank configuration
8-bit column address
DQMU
A13 (BS1)
A12 (BS0)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ15 to DQ0
CKE
CLK
DQML
address: A13/A12
Column address
input: A11 to A0
input: A7 to A0
Row address
Bank select