HD6432670 Hitachi, HD6432670 Datasheet - Page 245

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.7.5
When the DCTL pin is fixed to 1, synchronous clock (SDRAM ) is output from the &6 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to 1 or 2,
SDRAM is 90° phase shift from . Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between
and SDRAM . When the frequency multiplication factor of the PLL circuit is 4, the phase of
SDRAM and that of are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAM of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to 1 or 2.
Note: SDRAM output timing is shown when the frequency multiplication factor of the PLL
6.7.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Figure 6.43 Relationship between and SDRAM (when PLL frequency multiplication
circuit is 1 or 2.
Synchronous DRAM Clock
Basic Operation Timing
SDRAMø
ø
c1
and two T
factor is 1 or 2)
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
1/4 T cyc (90˚)
Rev. 2.0, 04/02, page 199 of 906
r
(row address