HD6432670 Hitachi, HD6432670 Datasheet - Page 19

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

11.5 Interrupt Sources..........................................................................................................562
11.6 DTC Activation ........................................................................................................... 564
11.7 DMAC Activation........................................................................................................ 564
11.8 A/D Converter Activation ............................................................................................ 564
11.9 Operation Timing......................................................................................................... 565
11.10 Usage Notes................................................................................................................. 571
Section 12 Programmable Pulse Generator (PPG) ..........................................579
12.1 Features ....................................................................................................................... 579
12.2 Input/Output Pins ......................................................................................................... 581
12.3 Register Descriptions ................................................................................................... 581
12.4 Operation..................................................................................................................... 589
11.4.6 Phase Counting Mode ...................................................................................... 556
11.9.1 Input/Output Timing........................................................................................ 565
11.9.2 Interrupt Signal Timing.................................................................................... 568
11.10.1 Module Stop Mode Setting .............................................................................. 571
11.10.2 Input Clock Restrictions................................................................................... 571
11.10.3 Caution on Cycle Setting ................................................................................. 572
11.10.4 Contention between TCNT Write and Clear Operations.................................... 572
11.10.5 Contention between TCNT Write and Increment Operations ............................ 573
11.10.6 Contention between TGR Write and Compare Match ....................................... 574
11.10.7 Contention between Buffer Register Write and Compare Match ....................... 574
11.10.8 Contention between TGR Read and Input Capture............................................ 575
11.10.9 Contention between TGR Write and Input Capture........................................... 576
11.10.10 Contention between Buffer Register Write and Input Capture ....................... 576
11.10.11 Contention between Overflow/Underflow and Counter Clearing................... 577
11.10.12 Contention between TCNT Write and Overflow/Underflow.......................... 578
11.10.13 Multiplexing of I/O Pins .............................................................................. 578
11.10.14 Interrupts and Module Stop Mode ................................................................ 578
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)....................................... 582
12.3.2 Output Data Registers H, L (PODRH, PODRL) ............................................... 583
12.3.3 Next Data Registers H, L (NDRH, NDRL)....................................................... 584
12.3.4 PPG Output Control Register (PCR) ................................................................ 586
12.3.5 PPG Output Mode Register (PMR) .................................................................. 587
12.4.1 Output Timing................................................................................................. 590
12.4.2 Sample Setup Procedure for Normal Pulse Output............................................ 591
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) ......... 592
12.4.4 Non-Overlapping Pulse Output ........................................................................ 593
12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................. 594
12.4.6 Example of Non-Overlapping Pulse Output
12.4.7 Inverted Pulse Output ...................................................................................... 596
(Example of Four-Phase Complementary Non-Overlapping Output)................. 595
Rev. 2.0, 04/02, page xvii of xliv