HD6432670 Hitachi, HD6432670 Datasheet - Page 413

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
Figure 8.21 shows an example of block transfer mode transfer activated by the
level.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of write cycle.
ø
Address bus
DMA control
Channel
Figure 8.20 Example of Normal Mode Transfer Activated by
Acceptance after transfer enabling;
(As in [1],
pin sampling is performed in each cycle starting at the next rise of ø after the end of the
Idle
[1]
Minimum 3 cycles
Request
Bus release
pin low level is sampled at rise of ø, and request is held.)
[2]
Read
[3]
Request clearance period
Transfer source
DMA read
Write
DMA write
destination
Transfer
pin while acceptance via the
pin low level is sampled at rise of ø, and request is held.
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Read
Request clearance period
[6]
Rev. 2.0, 04/02, page 367 of 906
Transfer source
DMA read
Write
DMA write
destination
Transfer
Pin Low Level
Idle
pin is possible,
Acceptance
resumed
pin low level
[7]
Bus release
pin low