HD6432670 Hitachi, HD6432670 Datasheet - Page 30

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)............ 229
Figure 6.66 Example of Idle Cycle Operation (Write after Read)............................................ 230
Figure 6.67 Example of Idle Cycle Operation (Read after Write)............................................ 231
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)........................................ 232
Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0)......................... 232
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
Figure 6.77 Example of Idle Cycle Operation after DRAM Access (Write after Read)
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
Figure 6.79 Example of Idle Cycle Operation after Continuous
Figure 6.80 Example of Idle Cycle Operation after Continuous
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Figure 6.83 Example of Timing when Write Data Buffer Function is Used............................. 246
Figure 6.84 Bus Released State Transition Timing ................................................................. 249
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface .......... 250
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ..................................................................................... 256
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)............................................. 280
Figure 7.3 Operation in Sequential Mode ............................................................................... 287
Figure 7.4 Example of Sequential Mode Setting Procedure .................................................... 288
Figure 7.5 Operation in Idle Mode ......................................................................................... 289
Rev. 2.0, 04/02, page xxviii of xliv
(IDLC = 0, CAS Latency 2)................................................................................. 235
(IDLC = 1, CAS Latency 2)................................................................................. 236
(IDLC = 0, CAS Latency 2)................................................................................. 237
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) .......... 238
(IDLC = 0, RAST = 0, CAST = 0) ....................................................................... 238
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ...................................................... 239
Synchronous DRAM Space Read Access (Read between Different Area)
(IDLC = 0, CAS Latency 2)................................................................................. 240
Write Accesses to DRAM Space in RAS Down Mode ......................................... 243
Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode
(SDWCD = 1, CAS Latency 2)............................................................................ 244
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) ......... 233
(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 233
(CAS Latency 2) ................................................................................................ 234
Synchronous DRAM Space Write Access
(IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) ......................................... 241