HD6432670 Hitachi, HD6432670 Datasheet - Page 434

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Table 8.4
Interrupt
EXDMTEND0
EXDMTEND1
EXDMTEND2
EXDMTEND3
Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant
channel, and can be sent to the interrupt controller independently. The relative priority order of the
channels is determined by the interrupt controller (see table 8.4).
Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever
the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of
the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in EDACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in EDMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
Rev. 2.0, 04/02, page 388 of 906
Interrupt Sources and Priority Order
EDIE bit
IRF bit
Interrupt source
Transfer end indicated by channel 0 transfer counter
Channel 0 source address repeat area overflow
Channel 0 destination address repeat area overflow
Transfer end indicated by channel 1 transfer counter
Channel 1 source address repeat area overflow
Channel 1 destination address repeat area overflow
Transfer end indicated by channel 2 transfer counter
Channel 2 source address repeat area overflow
Channel 2 destination address repeat area overflow
Transfer end indicated by channel 3 transfer counter
Channel 3 source address repeat area overflow
Channel 3 destination address repeat area overflow
Figure 8.45 Transfer End Interrupt Logic
Transfer end interrupt
Interrupt Priority
High
Low