HD6432670 Hitachi, HD6432670 Datasheet - Page 942

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Item
10.2.4 Pin Functions
P21/PO1/TIOCB3/(
10.2.4 Pin Functions
P20/PO0/TIOCA3/(
10.3.6 Pin Functions
P35/SCK1/SCL0/(
(CKE
10.6.4 Pin Functions
P63/TMCI1/
10.6.4 Pin Functions
P62/TMCI0/
10.6.4 Pin Functions
P61/TMRI1/
10.6.4 Pin Functions
P60/TMRI0/
10.14.4 Pin Functions
PF0/
10.15.5 Pin Functions
PG3/CS3/RAS3*/CAS*,
PG2/CS2/RAS2*/RAS*
14.6.2 Contention
between Timer Counter
(TCNT) Write and
Increment
16.3.2 I2C Bus Control
Register B (ICCRB)
Rev. 2.0, 04/02, page 896 of 906
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491
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629
714
Revisions (See Manual for Details)
The values of MD3 to MD0 in the subordinated table
amended.
(Error) B'0001 to B'0011
The values of MD3 to MD0 in the subordinated table
amended.
(Error) B'0001 to B'01xx
(Correction)
RMTS2 to RMTS0 in DRAMCR, bit OES in PFCR2, and bit
P35DDR.
Note added.
When used as the external clock input pin for the TMR, its pin
function should be specified to the external clock input by the
CKS2 to CKS0 bits in TCR_1.
Note added.
When used as the external clock input pin for the TMR, its pin
function should be specified to the external clock input by the
CKS2 to CKS0 bits in TCR_1.
Note added.
When used as the counter reset input pin for the TMR, both
the CCLR1 and CCLR0 bits in TCR_1 should be set to 1.
Note added.
When used as the counter reset input pin for the TMR, both
the CCLR1 and CCLR0 bits in TCR_1 should be set to 1.
(Correction)
If a timer counter clock pulse is generated during the next
cycle after the T2 state of a TCNT write cycle,
Bit
5
PGnDDR
Pin function PGn
Operating
mode
Description
A/D Start
Clearing this bit to 0 stops A/D conversion, and
the A/D converter enters wait state. When this bit
is set to 1 by software, TPU (trigger), TMR
(trigger), or the ADTRG pin, A/D conversion starts.
This bit remains set to 1 during A/D conversion. In
single mode, cleared to 0 automatically when
conversion on the specified channel ends. In
scan mode, conversion continues sequentially on
the specified channels until this bit is cleared to 0
by a reset, or a transition to hardware standby
mode or software.
input
0
bits CKE0 and CKE1 in SCR, bits OEE and
bit EXPE, bit WAITE in BCR, and bit PF0DDR.
PGn
output
1
PGn
input
0
(Correction) B'0000
PGn
output
(Correction) B'0000
1
PGn
input
3*, 7
0
output output output output
1
*
*