HD6432670 Hitachi, HD6432670 Datasheet - Page 406

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

of transfers is carried out, a block-size transfer is always executed, except in the event of a reset,
transition to standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an interrupt request source occurs.
If the EDIE bit in EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the DMA transfer bus cycle in which the source generating the interrupt
occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupts Sources.
8.4.8
The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.
Table 8.3 shows the EXDMAC channel priority order.
Table 8.3
Channel
Channel 0
Channel 1
Channel 2
Channel 3
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.
Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If
transfer requests for different channels are issued during a transfer operation, the highest-priority
channel (excluding the currently transferring channel) is selected. The selected channel begins
transfer after the currently transferring channel releases the bus. If there is a bus request from a bus
mastership other than the EXDMAC at this time, a cycle for the other bus mastership is initiated.
If there is no other bus request, the bus is released for one cycle.
Channels are not switched during burst transfer or transfer of a block in block transfer mode.
Rev. 2.0, 04/02, page 360 of 906
Channel Priority Order
EXDMAC Channel Priority Order
Priority
High
Low