HD6432670 Hitachi, HD6432670 Datasheet - Page 299

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

External Bus Release: When the
while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.13
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.14
6.14.1
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of
the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the
all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus
controller and I/O ports. In this state, the external bus release function is halted. To use the
external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0.
Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is
executed in the external bus released state, the transition to all-module-clocks-stopped mode is
deferred and performed until after the bus is recovered.
6.14.2
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.14.3
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the
refresh/auto refresh request is issued.
Note: In the H8S/2678 Series, the auto refresh control is not supported.
Bus Controller Operation in Reset
Usage Notes
External Bus Release Function and All-Module-Clocks-Stopped Mode
External Bus Release Function and Software Standby
External Bus Release Function and CBR Refreshing/Auto Refreshing
%5(4
pin goes low and an external bus release request is issued
%5(42
signal to be output when a CBR
%5(4
Rev. 2.0, 04/02, page 253 of 906
goes low in this mode,