HD6432670 Hitachi, HD6432670 Datasheet - Page 411

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

transfer activated by the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and
of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the
edge.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start;
[4], [7] When
ø
Address bus
DMA control
Channel
Figure 8.18 Example of Normal Mode Transfer Activated by
Acceptance after transfer enabling;
(As in [1],
Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode
pin sampling is performed in each cycle starting at the next rise of ø after the end of the
Idle
[1]
Minimum 3 cycles
Request
pin high level has been sampled, acceptance is resumed after completion of write cycle.
Bus release
pin low level is sampled at rise of ø, and request is held.)
[2]
pin high level sampling is started at rise of ø.
Read
[3]
Request clearance period
Transfer source
DMA read
pin falling edge.
pin high level sampling for edge sensing is started. If
Write
pin low level sampling is performed again; this sequence
DMA write
pin while acceptance via the
destination
Transfer
pin low level is sampled at rise of ø, and request is held.
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Rev. 2.0, 04/02, page 365 of 906
Read
[6]
Request clearance period
Transfer source
DMA read
Write
Pin Falling Edge
DMA write Bus release
destination
Transfer
pin is possible,
Idle
Acceptance
resumed
[7]
pin falling