HD6432670 Hitachi, HD6432670 Datasheet - Page 243

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.7.3
If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous
DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;
if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.
In 16-bit continuous synchronous DRAM space, 16-bit configuration synchronous DRAM can be
connected directly.
In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is
enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of
the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
6.7.4
Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the
synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.
Since the &6 to &6 pins are in the input state after a reset, set DDR to 1 when 5$6 , &$6 , and
:( signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR
register to 1 when the CKE signal is output.
Data Bus
Pins Used for Synchronous DRAM Interface
Rev. 2.0, 04/02, page 197 of 906