HD6432670 Hitachi, HD6432670 Datasheet - Page 420

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,
an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it
continues (as a burst) until the transfer end condition is satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Rev. 2.0, 04/02, page 374 of 906
ø pin
Bus cycle
Current
channel
Other
channel
transfer
request
(
ø pin
Bus cycle
CPU
operation
)
single cycle
CPU cycle
EXDMA
External
space
Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode
Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode
1 cycle
Bus
release
(Contention with Another Channel/Single Address Mode)
EXDMA single
single cycle
transfer cycle
EXDMA
External space
(CPU Cycles/Single Address Mode)
Bus
release
single cycle
1 bus cycle
CPU cycle
EXDMA
1 cycle
Bus
release
EXDMA single
transfer cycle
Higher-priority channel EXDMA cycle
External space
CPU cycle
Last transfer cycle
EXDMA single
transfer cycle
1 cycle
Bus
release
External space
single cycle
EXDMA
CPU cycle
Bus
release