HD6432670 Hitachi, HD6432670 Datasheet - Page 177

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals ( &6Q ) and address signals is to be extended. Extending the assertion period of the
&6Q and address signals allows flexible interfacing to external I/O devices.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
CSACRH
CSACRL
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
Bit Name
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
$ $
Assertion Period Control Registers H, L (CSACRH, CSACRL)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
&6
Control 1
These bits specify whether or not the T
to be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the
and address assertion period (T
extended
1: In area n basic bus interface access, the
and address assertion period (T
Description
&6
Control 2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
&6Q
inserted before the normal access cycle.
0: In area n basic bus interface access, the
and address assertion period (T
extended
1: In area n basic bus interface access, the
and address assertion period (T
and Address Signal Assertion Period
and Address Signal Assertion Period
and address signals are asserted, is
h
cycle, in which only the
Rev. 2.0, 04/02, page 131 of 906
t
cycle, in which only the
h
h
t
t
) is not
) is extended
) is not
) is extended
&6Q
(n = 7 to 0)
(n = 7 to 0)
h
t
cycle
cycle is
and
&6Q
&6Q
&6Q
&6Q