HD6432670 Hitachi, HD6432670 Datasheet - Page 399

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the
block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify
the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256
can be specified. During transfer of a block, transfer requests for other higher-priority channels are
held pending. When transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus mastership during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The
ends. The
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 8.4.6, Repeat Area Function, for details.
Transfer conditions:
Transfer conditions:
Bus cycle
Bus cycle
Dual address mode, auto request mode
Single address mode, external request mode
signal is output for each block transfer in the DMA transfer cycle in which the block
Figure 8.7 Examples of Timing in Normal Transfer Mode
signal is output once for one transfer request (for transfer of one block).
Read
transfer cycle
EXDMA
Write
EXDMA
Read
Last EXDMA
transfer cycle
EXDMA
Write
Rev. 2.0, 04/02, page 353 of 906