HD6432670 Hitachi, HD6432670 Datasheet - Page 335

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.
Figure 7.6 shows an example of the setting procedure for idle mode.
Register
23
23
H'FF
15
MAR
15
Register Functions in Idle Mode
ETCR
MAR
IOAR
0
0
0
Figure 7.5 Operation in Idle Mode
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Rev. 2.0, 04/02, page 289 of 906
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
IOAR