HD6432670 Hitachi, HD6432670 Datasheet - Page 686

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
1
0
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
5
4
Rev. 2.0, 04/02, page 640 of 906
Bit Name
CKS1
CKS0
Bit Name
GM
BLK
PE
O/
Initial Value
0
0
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0:
These bits select the clock source for the on-chip
baud rate generator.
00: ø clock (n = 0)
01: ø/4 clock (n = 1)
10: ø/16 clock (n = 2)
11: ø/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of one bit), and clock
output control mode addition is performed. For
details, refer to section 15.7.8, Clock Output
Control.
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 15.7.3, Block Transfer Mode.
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. In Smart Card
interface mode, this bit must be set to 1.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card
interface mode, refer to section 15.7.2, Data
Format (Except for Block Transfer Mode).