HD6432670 Hitachi, HD6432670 Datasheet - Page 837

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

22.2
22.2.1
When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to
clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32)
specified by bits SCK2 to SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the 5(6 pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the 67%< pin is driven low, a transition is made to hardware standby mode.
22.2.2
Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in
SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of
the CPU’s internal registers are retained. Other peripheral functions do not stop.
Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the 5(6 , or 67%< pins.
Exiting Sleep Mode by Interrupts:
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Exiting Sleep Mode by 5(6 pin:
Setting the 5(6 pin level low selects the reset state. After the stipulated reset input duration,
driving the 5(6 pin high starts the CPU performing reset exception processing.
Exiting Sleep Mode by 67%< Pin:
When the 67%< pin level is driven low, a transition is made to hardware standby mode.
Operation
Clock Division Mode
Sleep Mode
Rev. 2.0, 04/02, page 791 of 906