HD6432670 Hitachi, HD6432670 Datasheet - Page 359

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes,
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.10
Single Address Mode (Read): Figure 7.26 shows a transfer example in which
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
ø
Address
bus
DMA
control
Channel
Figure 7.25 Example of
Acceptance after transfer enabling; the
and the request is held.
(As in [1], the
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the
DMA Bus Cycles (Single Address Mode)
Idle
Bus release
[1]
Request
of 2 cycles
Minimum
pin low level is sampled while acceptance by means of the
[2]
Read
[3]
pin low level is sampled on the rising edge of ø, and the request is held.)
Transfer source
Request clear period
DMA
read
Write
1 block transfer
Pin Low Level Activated Block Transfer Mode Transfer
Transfer destination
DMA
write
Acceptance resumes
Dead
pin low level is sampled on the rising edge of ø,
[4]
Request
DMA
dead
of 2 cycles
Minimum
Idle
[5]
release
Bus
Read
[6]
Transfer source
Request clear period
DMA
read
Rev. 2.0, 04/02, page 313 of 906
Write
1 block transfer
Transfer destination
DMA
write
Dead
pin low level
Acceptance resumes
pin is
DMA
dead
output is
[7]
Idle
release
Bus