HD6432670 Hitachi, HD6432670 Datasheet - Page 367

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.5.13
When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus
release cycle.
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC
ø
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.34 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Idle
release
Request clear
Rev. 2.0, 04/02, page 321 of 906
Bus
Read
DMA read
Channel 1 transfer
Write
DMA write
Read
DMA
read