HD6432670 Hitachi, HD6432670 Datasheet - Page 442

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
0
Legend:
9.2.2
MRB selects the DTC operating mode.
Bit
7
6
5
4
to
0
9.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
Rev. 2.0, 04/02, page 396 of 906
X : Don’t care
Bit Name
Sz
Bit Name
CHNE
DISEL
CHNS
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
Initial Value
Undefined
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
R/W
Description
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to 9.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTCER
is not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.