HD6432670 Hitachi, HD6432670 Datasheet - Page 838

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

22.2.3
Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM
data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the high-
impedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins ,54 to ,54 ), or by means of the 5(6 pin or 67%< pin. Setting the SSI bit
in SSIER to 1 enables ,54 to ,54 to be used as software standby mode clearing sources.
Clearing with an Interrupt:
When an NMI or IRQ0 to IRQ15 interrupt request signal is input, clock oscillation starts, and after
the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire
LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ15 is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Clearing with the 5(6 Pin:
When the 5(6 pin is driven low, clock oscillation is started. At the same time as clock oscillation
starts, clocks are supplied to the entire LSI. Note that the 5(6 pin must be held low until clock
oscillation stabilizes. When the 5(6 pin goes high, the CPU begins reset exception handling.
Clearing with the 67%< Pin:
When the 67%< pin is driven low, a transition is made to hardware standby mode.
Rev. 2.0, 04/02, page 792 of 906