HD6432670 Hitachi, HD6432670 Datasheet - Page 297

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.12
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
6.12.1
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus mastership is as follows:
An internal bus access by internal bus masters except the EXDMAC and external bus release, a
refresh when the CBRM bit is 0, and an external bus access by the EXDMAC can be executed in
parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to
DRAM space by an internal bus master can be executed simultaneously, there is no relative order
of priority for these two operations.
6.12.2
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
(High) EXDMAC > DMAC > DTC > CPU (Low)
(High) Refresh > EXDMAC > External bus release (Low)
(High) External bus release > External access by internal bus master except EXDMAC (Low)
Bus Arbitration
Operation
Bus Transfer Timing
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