HD6432670 Hitachi, HD6432670 Datasheet - Page 235

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

A setting can be made in bits RCW1 and RCW0 in REFCR to delay 5$6 signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the 5$6 signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.37 shows the timing when bits RCW1 and RCW0 are set.
Depending on the DRAM used, modification of the :( signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example
of the timing when the CBRM bit is set to 1. In this case the &6 signal is not controlled, and
retains its value prior to the start of the refresh period.
ø
(
,
ø
)
(
,
)
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)
T
Rp
Figure 6.36 CBR Refresh Timing
Figure 6.37 CBR Refresh Timing
T
Rp
T
Rrw
T
Rr
T
Rr
T
Rc1
Rev. 2.0, 04/02, page 189 of 906
T
Rc1
T
Rc2
T
Rc2