HD6432670 Hitachi, HD6432670 Datasheet - Page 278

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2 (not available in the H8S/2678
Series), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in
different areas, for example, if the second read is a full access to DRAM space, only a T
inserted, and a T
Rev. 2.0, 04/02, page 232 of 906
Address bus
(area A)
(area B)
Figure 6.68 Relationship between Chip Select (
Figure 6.69 Example of DRAM Full Access after External Read
Overlap period between
and
ø
i
cycle is not. The timing in this case is shown in figure 6.69.
Address bus
(a) No idle cycle insertion
Data bus
T
may occur
(ICIS1 = 0)
1
Bus cycle A
ø
T
2
T
3
Bus cycle B
T
T
1
(area B)
1
External read
T
T
2
2
(CAST = 0)
Address bus
T
3
(area A)
(area B)
T
p
ø
DRAM space read
T
r
T
(b) Idle cycle insertion
1
Bus cycle A
$ $
(ICIS1 = 1, initial value)
T
T
c1
2
) and Read (
T
T
3
c2
Idle cycle
T
i
Bus cycle B
# #
T
1
)
T
2
p
cycle is