HD6432670 Hitachi, HD6432670 Datasheet - Page 259

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Note, however, the next continuous synchronous DRAM space access is a full access if:
There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.
a refresh operation is initiated in the RAS down state
self-refreshing is performed
the chip enters software standby mode
the external bus is released
the BE bit is cleared to 0
the mode register of the synchronous DRAM is set
Precharge-sel
DQMU, DQML
Address bus
Data bus
CKE
Figure 6.53 Example of Operation Timing in RAS Down Mode
ø
PALL ACTV READ
Continuous synchronous
DRAM space read
Column
address
T
p
address
address
Row
Row
T
r
(BE = 1, CAS Latency 2)
T
c1
Column address
T
cl
T
c2
High
NOP
External
space read
External address
External address
T
1
T
2
Rev. 2.0, 04/02, page 213 of 906
READ
Continuous synchronous
DRAM space read
T
c1
Column address 2
T
cl
NOP
T
c2