HD6432670 Hitachi, HD6432670 Datasheet - Page 396

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

8.4.3
Auto Request Mode: In auto request mode, transfer request signals are automatically generated
within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in
transfer between two memories, or between a peripheral module that is not capable of generating
transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to
1 in EDMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
External Request Mode: In external request mode, transfer is started by a transfer request signal
(
DMA transfer is enabled (EDA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the
sensing can be selected for the
sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).
Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance
to be output from the
processing has been started in response to a single external request. The
the external device to determine the timing of
provide handshaking between the transfer request source and the EXDMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the
only once for a one-block transfer, since the transfer request via the
unit.
8.4.4
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
Cycle Steal Mode: In cycle steal mode, the EXDMAC releases the bus at the end of each transfer
of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC
takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This
procedure is repeated until the transfer end condition is satisfied.
Rev. 2.0, 04/02, page 350 of 906
) from a device external to this LSI. DMA transfer is started when
DMA Transfer Requests
Bus Modes
K pin. The
pin by means of the EDREQS bit in EDMDR (low level
signal is output when acceptance and transfer
pin. Either falling edge sensing or low level
signal negation, and makes it possible to
pin is for a block
signal enables
signal is output
is input while