HD6432670 Hitachi, HD6432670 Datasheet - Page 370

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
7.6
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt
Name
DMTEND0A
DMTEND0B
DMTEND1A
DMTEND1B
Rev. 2.0, 04/02, page 324 of 906
Interrupt Sources
Clear FAE bit to 0
Stop the channel
Initialize DMACR
operation halted
address mode
Initialization;
Figure 7.37 Example of Procedure for Clearing Full Address Mode
Clearing full
Interrupt Source
Short Address Mode
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0B
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1B
[1]
[2]
[3]
[1] Clear both the DTE bit and DTME bit in
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
DMABCRL to 0, or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0. Also clear the corresponding
DTIE bit to 0 at the same time.
Full Address Mode
Interrupt due to end of
transfer on channel 0
Interrupt due to break in
transfer on channel 0
Interrupt due to end of
transfer on channel 1
Interrupt due to break in
transfer on channel 1
Interrupt
Priority Order
High
Low

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