HD6432670 Hitachi, HD6432670 Datasheet - Page 265

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected externally and DRAM data is to be retained in sleep mode, the
ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PLL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.
6.7.14
To use synchronous DRAM, mode must be set after power-on. to set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
DQMU, DQML
Precharge-sel
Address bus
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
SDRAM
Data bus
CKE
ø
ø
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Mode Register Setting of Synchronous DRAM
Software
standby
NOP
T
Rc2
T
Rp1
T
Rp2
Column address
PALL
T
p
Row address
Row address
Continuous synchronous DRAM space write
ACTV
Rev. 2.0, 04/02, page 219 of 906
T
r
T
NOP
c1
Column address
NOP
T
cl
NOP
T
c2