HD6432670 Hitachi, HD6432670 Datasheet - Page 307

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.3.4
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B).
In short address mode, channels A and B operate independently, and in full address mode,
channels A and B operate together. The bit functions in the DMACR registers differ according to
the transfer mode.
Short Address Mode:
Bit
7
6
DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit Name
DTSZ
DTID
DMA Control Registers (DMACRA and DMACRB)
Initial Value
0
0
R/W
R/W
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
1: MAR is decremented after a data transfer
When DTSZ = 0, MAR is incremented by 1
When DTSZ = 1, MAR is incremented by 2
When DTSZ = 0, MAR is decremented by 1
When DTSZ = 1, MAR is decremented by 2
(Initial value)
Rev. 2.0, 04/02, page 261 of 906