HD6432670 Hitachi, HD6432670 Datasheet - Page 38

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Figure 22.3 Hardware Standby Mode Timing......................................................................... 795
Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit ............................................................................................ 840
Figure 24.2 System Clock Timing.......................................................................................... 841
Figure 24.3 SDRAM Timing* ............................................................................................. 842
Figure 24.4 (1) Oscillation Stabilization Timing..................................................................... 842
Figure 24.4 (2) Oscillation Stabilization Timing..................................................................... 843
Figure 24.5 Reset Input Timing ............................................................................................. 844
Figure 24.6 Interrupt Input Timing ........................................................................................ 845
Figure 24.7 Basic Bus Timing: Two-State Access .................................................................. 849
Figure 24.8 Basic Bus Timing: Three-State Access ................................................................ 850
Figure 24.9 Basic Bus Timing: Three-State Access, One Wait................................................ 851
Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) .............. 852
Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............. 853
Figure 24.12 Burst ROM Access Timing: One-State Burst Access ......................................... 854
Figure 24.13 Burst ROM Access Timing: Two-State Burst Access......................................... 855
Figure 24.14 DRAM Access Timing: Two-State Access ........................................................ 856
Figure 24.15 DRAM Access Timing: Two-State Access, One Wait........................................ 857
Figure 24.16 DRAM Access Timing: Two-State Burst Access ............................................... 858
Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) ................................... 859
Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... 860
Figure 24.19 DRAM Access Timing: Three-State Burst Access ............................................. 861
Figure 24.20 CAS-Before-RAS Refresh Timing..................................................................... 862
Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 862
Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ............ 862
Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ............ 863
Figure 24.24 External Bus Release Timing ............................................................................ 863
Figure 24.25 External Bus Request Output Timing................................................................. 864
Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. 865
Figure 24.27 Synchronous DRAM Self-Refresh Timing......................................................... 866
Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2) ........................................... 867
Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access...... 869
Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access.... 870
Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing...................................... 871
Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing........................................ 871
Figure 24.33 EXDMAC EDRAK Output Timing................................................................... 871
Figure 24.34 I/O Port Input/Output Timing ............................................................................ 873
Figure 24.35 PPG Output Timing .......................................................................................... 873
Figure 24.36 TPU Input/Output Timing ................................................................................. 873
Figure 24.37 TPU Clock Input Timing................................................................................... 874
Figure 24.38 8-Bit Timer Output Timing ............................................................................... 874
Figure 24.39 8-Bit Timer Clock Input Timing........................................................................ 874
Figure 24.40 8-Bit Timer Reset Input Timing......................................................................... 874
Rev. 2.0, 04/02, page xxxvi of xliv