HD6432670 Hitachi, HD6432670 Datasheet - Page 327

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
7.3.7
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit
7
6
5
4
3
to
0
Bit Name
TEE1
TEE0
DMA Terminal Control Register (DMATCR)
Initial Value
0
0
0
0
All 0
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Enable 1
Enables or disables transfer end pin 1 (
output.
0:
1:
Transfer End Enable 0
Enables or disables transfer end pin 0 (
output.
0:
1:
Reserved
These bits are always read as 0 and cannot be
modified.
pin output disabled
pin output enabled
pin output disabled
pin output enabled
Rev. 2.0, 04/02, page 281 of 906
)
)

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