HD6432670 Hitachi, HD6432670 Datasheet - Page 695

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Bit
0
15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous
Mode
Clocked
Synchronous
Mode
Smart Card
Interface Mode
Note: B: Bit rate (bit/s)
CKS1
0
0
1
1
Bit Name
SMIF
N: BRR setting for baud rate generator (0
ø: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
Bit Rate Register (BRR)
0
1
0
1
CKS0
Bit Rate
B =
B =
B =
Initial Value
0
64
S
8
2
2
2
ø
2n-1
ø
ø
2n-1
2n-1
n
0
1
2
3
10
10
10
(N + 1)
(N + 1)
6
6
6
(N + 1)
R/W
R/W
Description
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart card interface mode
Error
Error (%) = {
Error (%) = {
N
BCP1
0
0
1
1
255)
SMR Setting
B
B
64
Rev. 2.0, 04/02, page 649 of 906
S
BCP0
0
1
0
1
ø
ø
2
2
2n-1
2n-1
10
10
6
6
(N + 1)
(N + 1)
32
64
372
256
S
-1 }
-1 }
100
100

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